Circuit timing in modern VLSI design is greatly impacted by the placement of circuits within the design image. The relative physical placements impact the wire delays and circuit delays due to changes in length as well as changes in capacitance and resistance between the circuits. It is therefore important to know or estimate the circuit placements during timing closure, allowing circuit optimizations to assess and measure the viability of cell changes. Such methods are crucial in helping prevent optimizations from creating congestion or cell overlaps which can counteract timing closure efforts.
Timing closure tools rely on a variety of estimations throughout the timing closure process, and operations in the physical placement domain also leverage this behavior. Tools use the approximations to help reduce computation complexity and decrease turn around time. During the initial phases of optimization a design will usually have a multitude of timing problems that require attention. Using estimates allows for fast optimization, and helps take down gross problems quickly. As the timing of the chip improves and the timing closure flow progresses, automated flows increase the accuracy of their estimations to ensure the tool is working on the right problems.
Placement driven synthesis provides multiple placement techniques allowing circuit transformations to repair timing violations, including estimated modes and high accuracy modes. One estimated technique is the bin-based placement model. This model divides the placement image into a collection of regions containing circuits, called bins. The bin based model allows for a fast computation of bin size and provides a mechanism to compute the relative circuit location which can be used by steiner wire calculations as a first order approximation for full chip timing. This model allows optimizations to make relatively quick decisions on whether a particular section of a chip will support an increase of physical cell size. A placement legalization Step is required after making any changes to realize the final circuit placements.
As timing closure progresses, it becomes advantageous to accurately predict the impact of placement related changes on the design. This can be achieved by restricting placement legalization and using a high accuracy incremental exact-placement model. The high accuracy placement technique available to optimizations is exact placement. In this exact placement, model the optimization insert cells into existing open-placement locations. The placements are legal and will not produce overlaps. The benefit of this technique is that the optimization can evaluate the real placements that allow measuring the timing to a high degree of accuracy. Because the method does not require legalization there are no side effects to existing logic. The drawback of that technique is that localized areas of congestion and physical image fragmentation can make it difficult to find existing open placement locations, especially for larger circuit sizes.
FIG. 1A of the prior art illustrates a section of the chip that is under optimization using the exact placement model. In the example, the cell labeled “O” is optimized and a circuit optimization determines that a buffer is needed to repair a violation. In the illustration the “x” mark denotes the requested target placement location of the new cell, whereas the cell labeled “A” is the desired size of the open placement location.
FIG. 1B shows a prior art exemplary outcome of an optimization using an exact placement model. In the example, the placement tool was able to find an open placement location near the target location. Upon finding the open placement location, the optimization can decide whether the open placement location is suitable to repair the violation under consideration.
Although the estimated model offers a fast way to optimize circuits with consideration to the physical domain, the primary drawback of the model is that it requires circuit legalization to correct overlaps. The legalization may have deleterious effects on the critical path timing.
A drawback of the exact placement model is that it requires open space in the existing placement image for new additions or modifications within proximity to the net under optimization. The open space can be unfounded due to congestion or design fragmentation. In other scenarios, the open space may be too far outside of the wiring bounding box, causing the optimization to evaluate a free location that would otherwise fail due to electrical or timing constraints.